The present invention relates in general to the fabrication of integrated circuits, and in particular to integrated circuit structures having damascene trench gates and local interconnects formed in a single process, and methods of fabricating such integrated circuit structures.
Integrated circuit manufacturers continually strive to scale down semiconductor devices in integrated circuit chips. By scaling down semiconductor devices, greater speed and capacity can be realized while reducing power consumption of the chip. For example, in order to provide increased capacity in memory chips such as SRAM, it is highly desirable to shrink the size of each memory cell as much as possible without significantly affecting performance. This can be accomplished by shrinking the size of each component that forms each memory cell, packing the components closer together, or both.
Further, as integrated circuits are scaled down, the complexity of fabricating the components that make up the devices continues to increase. With the increase in complexity also comes an increase in the cost of fabricating the integrated circuits. For example, as memory cells in SRAM continue to shrink, undesirable variations between desired results and actual results become a limiting factor because of the inherent limitations in many processes employed in the course of manufacturing. For example, precision limits in photolithography, and deposition processes affect production parameters.
Also, every masking step that is performed during fabrication dramatically increases the cost of manufacturing a given device. For example, in a typical damascene gate structure, three or more deposition and planarizing steps are required.
Therefore, there is a continuing need for a structure, process and method of fabrication that allows consistent and reliable formation of damascene gates and interconnects using minimal manufacturing processes.